DFT

Design for Testability (DFT) consists of IC design techniques that add testability features to a hardware product design. The added features make it easier to develop and apply manufacturing tests to the designed hardware. These methods are targeted for making it easier to develop and apply tests to the actual hardware & these tests in turn help catch manufacturing defects like stuck at 0, 1 faults, etc. DFT uses SCAN, ATPG and BIST techniques to add testability to Hardware design.

DFT Training covers

• Complete aspects of testability flow including testability basics,

• SOC Scan Architecture,

• different types of scan

• ATPG DRC Debug

• ATPG Simulation debug

• DFT diagnosis.

• JTAG, ATPG, scan, JTAG, LogicBIST, MemoryBIST and test compression techniques