Synthesis Training

Synthesis course covers methods of converting design RTL into logic gates.

Below Topics will be covered in Synthesis Training

Introduction to synthesis.

• Reading RTL in HDL form, dotlibs, SDC


• Different types of RTL constructs


• Analyzing dotlib files


• Understanding DesignWare components and Logical Operators


• Clock gating insertion for reducing Dynamic power post CTS


• Creating list of dont_touch and dont_use cells


• Technology mapped Synthesis and optimization


• Scan Insertion techniques

Quality Checks in Synthesis : Timing & Constraints validation

• Checking Design for number of instances, area estimate


• Check clock reaching clock pins of flops, unclocked flops


• Time borrowing concepts for latch based paths


• Constraints on logical hierarchy boundaries


• Setting Max Transition, Max Capacitance, Max Fanout


• Push down and pull up timing constraints


• Master clocks and generated clocks in design


• Estimating uncertainty values, input and output delays in SDC


• False path, Multi cycle path exceptions.


• Disabling timing loops in design

Different classes of VTs

Leakage variants of standard cells LVT, RVT, HVT

Formal verification check

Logical Equivalence Checking fundamentals (Top level and Hierarchical)